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Old 10-05-2007, 07:42 AM
Matt_G Matt_G is offline
Join Date: Jul 2000
Location: Brisbane, QLD, Australia
Posts: 590
Default Re: 7.3.1cs4 & cs5 Clocking Bug

One other thing - does this problem occur when using another clock source (SPDIF, ADAT, AES)? Also, have you tried it at other sample rates?
Ok just tried using AES 7-8 as the clock master which is where my HEDD is inserted on the 192. This worked flawlessly clocked from AES-EBU. So because we have established we can clock my 192 digi I/O off internal & external via AES-EBU it would appear that the problem lies with clocking externally from Wordclock.

I couldn't replicate this problem between 44.1 or 48k sessions clocked from wordclock, this seemed to be fine. So it seems it's only an issue going from 96k down to an 88.2k session or vice versa.

Mastering Engineer

Brisbane Australia
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